Senior ASIC Design Engineer Jobs

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14 Senior ASIC Design Engineer jobs found on Monster.

Jobs 1 to 14 of 14
As a member of our logic design team, you will be responsible for a portion of the design of an area and power efficient GPU, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, timing closure, power optimization, and supporting verification and implementation. Experience in high performance, low power arithmetic unit design is a plus. RESPONSIBILITIES - Own and be...
Intel OR
838096true838096falseSubmission for the position: Sr ASIC Design Engineer (Circuit Integration) - (Job Number: 737262)false838096falsetruehttps://intel.taleo.net/careersection/jobdetail.ftl?job=737262&lang=enSr ASIC Design Engineer (Circuit Integration)falseSr ASIC Design Engineer (Circuit Integration)737262Job Description: The Intel Custom Foundry group within TMG chartered to serve new products ...
Intel Corp. Hillsboro, OR
Job Description: The Intel Custom Foundry group within TMG chartered to serve new products is looking for qualified, talented individuals with alignment and experience in the required areas described below to join its ASIC Design Services Physical Design Methodology team to build the industry's next generation products. The key function is Circuit integration and ASIC implementation and timing si...
Micron Technology Minneapolis, MN, 55415
Req ID: 16481 As a Senior ASIC Design Engineer in Micron’s Advanced Controller Group, you will develop and verify cutting edge controllers which leverage Micron’s newest memory technology. You will be involved in the design and modeling of next generation memory interfaces for large mixed signal ASICs. This includes architecting, implementing, synthesizing and testing digital and custom circuit m...
Xelerated, Inc. Boise, ID, 83701
Candidate will perform physical design of complex, low power SOC ASICs in 40nm, 28nm and smaller processes. Major responsibilities will include but are not limited to: Parasitic extraction and static timing analysis. Floorplanning and hierarchical partitioning. Hierarchical and timing driven place & route. Power and noise analysis, clock tree analysis, signal integrity analysis. Physical verificat...
BSEE with 2+ years experience or MSEE with focus in ASIC physical design including: Static timing analysis and timing closure, signal integrity. Full chip floorplanning, place & route, physical verification. Experience in clock and power implementation methodologies and practices in low power designs. Understanding of hierarchical/timing driven layout methodologies and practices. Circuit level com...
Drive new memory system architectures from DRAM up. Explore architecture trade-offs in system performance, area, and power consumption. Develop interconnect (Network-on-chip - NOC) and memory hierarchies for high performance parallel computer architectures (system-on-a-chip SOC). Work with performance team to develop performance/power simulators, models and test suites. Design a memory sub-sys...
As a senior member of the SOC Design team you will be responsible for the following 1) Microarchitecture and design of RTL code for high performance (low latency, high bandwidth, high frequency), low area, and low power 2) Own all aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control bus logic for connectivity of IP b...
SENIOR ASIC DESIGN ENGINEER #1741601As a member of our logic design team, you will be responsible for a portion of the design of an area and power efficient GPU, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, timing closure, power optimization, and supporting verification and implementation. Experience in high performance, low power arithmetic unit design is a p...
•Participate in Cache micro architecture development from specifications found from architecture guideline and model analysis. •Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team. •Develop/debug RTL design of different sections of the cache. •Work with physical design team to close timing of the same. BS/MS/PhD in a releva...
Drive new memory system architectures from DRAM up. Explore architecture trade-offs in system performance, area, and power consumption. Develop interconnect (Network-on-chip - NOC) and memory hierarchies for high performance parallel computer architectures (system-on-a-chip SOC). Work with performance team to develop performance/power simulators, models and test suites. Design a memory sub-sys...
As a senior member of the SOC Design team you will be responsible for the following 1) Microarchitecture and design of RTL code for high performance (low latency, high bandwidth, high frequency), low area, and low power 2) Own all aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control bus logic for connectivity of IP b...
Xelerated, Inc. Santa Clara, CA, 95051
SoCPlatform group at Marvell is looking for an experienced Senior ASIC Design Engineer to work on a series of PCIe-related projects. PCIe domain knowledge is assumed. Ph.D. or MS in Electrical Engineering or Computer Engineering is required. The desirable candidate should have a minimum of 10 years industry ASIC design experience....
• 10+ years of experience in micro-architecture design • 10+ years of experience in Verilog RTL development experience in IP/SOC and ASIC environment • Must have a strong background in all aspects of ASIC implementation, especially with lint, synthesis, formal, CDC flow, and Static Timing Analysis, • Understanding of AMBA AXI protocol and PCI Express protocol are essential • Experience with FPGA i...

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IT Career Tools

Sr. ASIC Design Engineer

Salaries

$98,400.00 - $159,900.00
Typical Salary for Sr. ASIC Design Engineer
(42 Respondents)
Source: Monster.com Careerbenchmarking Tool

Education / Training

Master's
65%
Bachelor's
30%
Doctorate
5%
(20 Respondents)
Source: Monster.com Careerbenchmarking Tool

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